This invention relates to the logic structure of large scale integrated (LSI) digital circuits and more particularly to an LSI digital circuit logic structure in which additional logic functions are included for the purpose of facilitating the testing of the circuit.
Digital LSI circuits in which hundreds or even thousands of logic gates are fabricated on a single substrate chip, typically of silicon or sapphire, to form a complete system or subsystem are well known in the art. LSI technology provides a circuit with the advantages of lower power dissipation, higher performance, and lower cost. As a result, LSI circuits have found wide acceptance, for example, as logic and memory circuits in digital computers, communication systems and the like.
A conventional LSI circuit comprises a plurality of terminals typically in the form of metallic bonding-pads or beam leads on the chip used for applying input signals and for extracting output signals, a plurality of functional parts, each for performing a function or a set of functions and each comprising a network of logic gates and/or memory elements, the functional parts being interconnected at a multiplicity of internal nodes not directly connected to the terminals. Examples of such a circuit are the commercially available single-chip microprocessors.
In recent years both the packing density and complexity of LSI digital circuits have grown rapidly owing primarily to advances in metal-oxide-semiconductor (MOS) technology. Today, circuits such as the 16-bit microprocessor having in excess of 10,000 logic gates on a single chip are commercially available. A circuit having a gate count of 10,000 or greater is sometimes referred to as very large scale integrated (VLSI) circuit.
In general, as LSI digital circuits increase in complexity it becomes more difficult to perform functional tests on such circuits. Functional tests are used to determine whether a digital circuit performs its intended logical function. Since all integrated circuits are subject to fabrication defects and other failure mechanisms, a primary concern of both manufacturers and users of integrated circuits is the design of functional tests which are capable of detecting all possible logical faults which may occur in such circuits. For highly complex LSI circuits exhaustive functional tests are expensive to perform and in many cases impossible to design. Therefore, testing difficulties in LSI circuits give rise to higher manufacturing costs for such circuits as well as lower reliability for circuits which are not capable of being exhaustively tested.
Generally, integrated circuit functional tests can be divided into three types, namely diagnostic, production, and field site tests. Diagnostic tests are used to identify design errors and fabrication problems in a circuit when it is first manufactured. Thus, a diagnostic test is designed not only to detect logical faults in a circuit under test but also to locate and identify a detected fault.
Production tests are used to screen out faulty circuits after completion of fabrication as part of the manufacturing process. Production tests are designed to merely detect any logical faults in a circuit under test and are generally simpler and less time consuming than a diagnostic test.
Both diagnostic and production tests are normally performed at the manufacturing facility. The usual approach to such tests is to apply a sequence of binary patterns called test vectors to the input terminals of a circuit under test and to observe a resulting sequence of binary patterns called output pattern at the output terminals of the circuit. The output patterns which are generated by the circuit in response to the applied test vectors are compared to those expected from a fully functioning circuit; any disagreement between an observed output pattern and a corresponding expected output pattern indicates a faulty circuit. The percentage of all possible faults detectable by a test is commonly referred to as the fault coverage for the test.
In general, the length of a test vector sequence needed to maximize fault coverage increases with the complexity of the circuit tested. A typical production test for a particular prior art microprocessor, for example, contains tens of thousands of test vectors. A diagnostic test for the same circuit would have even more test vectors. The need for such lengthy test vector sequences makes such tests expensive to perform and makes necessary the use of powerful computer controlled test equipment for applying the test vectors. However, even with lengthy test vector sequences, the fault coverage of functional tests on many prior art LSI circuits is less than 100 percent.
Field-site tests of integrated circuits are typically performed while the circuits are situated in the systems in which they are used. Such tests may either be performed during troubleshooting of a malfunctioning system or, in the case of systems having built-in self-testing features, on a repetition basis while the system is operating. Because the test equipment used for field-site testing is generally less powerful than that used for production testing, field-site tests tend to be simpler than production tests. Consequently, the fault coverage of field-site tests are typically less than that of production tests.
It is well known that the problems of long test vector sequences and less than complete fault coverage in complex LSI circuits are directly related to the inaccessibility of signals on the internal nodes of such circuits. Unlike digital circuits implemented on printed circuit boards, the internal nodes of an integrated circuit cannot be probed during testing. Therefore, in many cases the responses of the various functional parts of an integrated circuit to applied test vectors cannot be directly observed, and an erroneous response from a functional part can be detected only if that response causes an erroneous output pattern. However, in many prior art LSI circuits a significant number of possible logical faults remain undetectable because the erroneous signals caused by such faults cannot be made to appear as erroneous output patterns. In such circuits, higher fault coverage and shorter test vector sequences would be possible if signals on selected internal nodes can be analyzed for errors from the terminals of the circuits.
One known approach for improving accessibility to signals on selected internal nodes of an integrated circuit is to provide additional terminals which are directly connected to such nodes. However, this approach is not practicable for LSI circuits where the number of selected internal nodes may far exceed the number of extra terminals (i.e., bonding pads or beam leads) which can be accommodated by the circuit chip.
Another prior art technique for improving accessibility to signals on internal nodes of LSI circuits is described in the references, "A Logic Design Structure for LSI Testability" by E. B. Eichelberger and T. N. Williams, Proceedings of the 14th Design Automation Conference, IEEE Catalog, No. 77 CH1216-1C, New Orleans, June 1977, pages 462-468, and "Level-Sensitive Scan Design Test Chips, Boards, Systems", by N. C. Berglund, Electronics, Vol. 52, No. 6, March 15, 1979, pages 108-110. The Eichelberger et al. and Berglund references describe, among other things, an LSI circuit logic structure in which a shift register latch (SRL) is associated with each selected internal node of the circuit. All the SRLs are connected to be operable as a single long shift register. The signals on the selected internal nodes are stored in their associated SRL and may be shifted out serially to a single output terminal under the control of a sequence of clock pulses.
However, the SRL technique has several deficiencies. Owing to the slowness of the conversion of the parallel data on the selected internal nodes to the serial data at the output terminal, the technique cannot be used to test a circuit which is operating at its full rated speed. Therefore, speed related faults (ac faults) may escape detection with the SRL method. Furthermore, error detection with the SRL method requires that the long bit-stream from the shift register must be examined on a bit-by-bit basis, making tests with this technique time consuming. Moreover, implementation of the SRL technique requires a large overhead in chip area, particularly where large numbers of internal nodes are accessed. Thus, the SRL technique tends to be expensive to implement.
Therefore, a need clearly exists for an LSI circuit logic structure for improving circuit testability which would permit rapid error analysis of data signals on a large number of internal nodes detecting ac as well as dc faults, and one which may be implemented with minimal overhead chip area.